Vertical offset in DSI (video mode) output image problem

Description

of how to solve vertical offset in output image as shown in the below image?
What’s the reason, it’s because of Vertical timing or other sources?

What MCU/Processor/Board and compiler are you using?

stm32f769igt6

What LVGL version are you using?

8.2

What do you want to achieve?

get rid off the vertical offset

What have you tried so far?

different vertical back porch & front porch. LTDC & DSI Different Clocks in Non-Burst Mode

Code to reproduce

Add a code snippet which can run in the simulator. It should contain only the relevant code that compiles without errors when separated from your main code base.

The code block(s) should be formatted like:

/*You code here*/

Screenshot and/or video

If possible, add screenshots and/or vid


eos about the current state.

Maybe not lvgl issue. STM DSI have this issue if LTDC and DSI starts async.