Psram cache write Back

How-to
1

Hi,

I would like to know how lvgl write(render buffer) before call “(*flush_cb)” function.

I am writing a driver and i need to know this, because maybe i will use psram memory which is external to the microcontroller.
To write in psram memory, the cpu write in the cache(inside cpu), but dma read directly from external psram memory (without going through cache), so i need tell cpu to update psram, so there are no inconsistencies in what is written in the cache and what is written in the psram memory.

For performance reasons i think that is more interesting just update the part of the buffer that lvgl lib wrote.

Here i am telling cpu to “write back” all allocated buffer(even the part that lib lvgl didn’t rendered):
Cache_WriteBack_Addr( (uint32_t)p_buffer_a, full allocated buffer ); // CPU writes data to PSRAM through DCache, data in PSRAM might not get updated, so write back.

Here i am telling cpu to “write back” only the part of the buffer that lvgl lib rendered ( considering lvgl lib renders like this, buffer[0] up to buffer[length] with no “spaces”, ie, 1d buffer.

Example:

#define bytes_per_pixel (LV_COLOR_SIZE / 8)

void display_flush( lv_disp_drv_t* drv, const lv_area_t* area, lv_color_t* color_map ) 
{  
    uint32_t length = (uint32_t) ( bytes_per_pixel * ( lv_area_get_width(area) * lv_area_get_height(area) ) );  
        
    if ( drv->buffer->buf_act == p_buffer_a )
    {           
        Cache_WriteBack_Addr( (uint32_t)p_buffer_a, lenght );
    
        lcd_write_pixels_a( length, area );      
        lv_disp_flush_ready( drv );
    }
    else if ( drv->buffer->buf_act == p_buffer_b )
    {   
        Cache_WriteBack_Addr( (uint32_t)p_buffer_b, lenght );
     
        lcd_write_pixels_b( length, area );        
        lv_disp_flush_ready( drv );
    }     
}

uint32_t length = (uint32_t) ( bytes_per_pixel * ( lv_area_get_width(area) * lv_area_get_height(area) ) );

Lvgl lib renders like this, buffer[0] up to buffer[length] with no “spaces”, ie, 1d buffer ?

Thanks.