Yes, I am.
xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:7048
load:0x40078000,len:14336
load:0x40080400,len:3672
entry 0x40080678
e[0;32mI (27) boot: ESP-IDF v4.4-dev-4-g73db14240-dirty 2nd stage bootloadere[0m
e[0;32mI (27) boot: compile time 13:33:00e[0m
e[0;32mI (28) boot: chip revision: 1e[0m
e[0;32mI (31) boot_comm: chip revision: 1, min. bootloader chip revision: 0e[0m
e[0;32mI (38) boot.esp32: SPI Speed : 40MHze[0m
e[0;32mI (43) boot.esp32: SPI Mode : DIOe[0m
e[0;32mI (48) boot.esp32: SPI Flash Size : 2MBe[0m
e[0;32mI (52) boot: Enabling RNG early entropy source...e[0m
e[0;32mI (58) boot: Partition Table:e[0m
e[0;32mI (61) boot: ## Label Usage Type ST Offset Lengthe[0m
e[0;32mI (68) boot: 0 nvs WiFi data 01 02 00009000 00006000e[0m
e[0;32mI (76) boot: 1 phy_init RF data 01 01 0000f000 00001000e[0m
e[0;32mI (83) boot: 2 factory factory app 00 00 00010000 00100000e[0m
e[0;32mI (91) boot: End of partition tablee[0m
e[0;32mI (95) boot_comm: chip revision: 1, min. application chip revision: 0e[0m
e[0;32mI (102) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=251dch (152028) mape[0m
e[0;32mI (164) esp_image: segment 1: paddr=00035204 vaddr=3ffb0000 size=03194h ( 12692) loade[0m
e[0;32mI (169) esp_image: segment 2: paddr=000383a0 vaddr=40080000 size=07c78h ( 31864) loade[0m
e[0;32mI (183) esp_image: segment 3: paddr=00040020 vaddr=400d0020 size=3cd6ch (249196) mape[0m
e[0;32mI (271) esp_image: segment 4: paddr=0007cd94 vaddr=40087c78 size=04c6ch ( 19564) loade[0m
e[0;32mI (286) boot: Loaded app from partition at offset 0x10000e[0m
e[0;32mI (286) boot: Disabling RNG early entropy source...e[0m
e[0;32mI (298) cpu_start: Pro cpu up.e[0m
e[0;32mI (298) cpu_start: Starting app cpu, entry point is 0x400810dce[0m
e[0;32mI (0) cpu_start: App cpu up.e[0m
e[0;32mI (314) cpu_start: Pro cpu start user codee[0m
e[0;32mI (314) cpu_start: cpu freq: 160000000e[0m
e[0;32mI (315) cpu_start: Application information:e[0m
e[0;32mI (319) cpu_start: Project name: lvgl-demoe[0m
e[0;32mI (324) cpu_start: App version: v2.0-55-gf2e80cbe[0m
e[0;32mI (330) cpu_start: Compile time: Feb 24 2021 14:12:55e[0m
e[0;32mI (336) cpu_start: ELF file SHA256: 64df4cef7e08853f...e[0m
e[0;32mI (342) cpu_start: ESP-IDF: v4.4-dev-4-g73db14240-dirtye[0m
e[0;32mI (349) heap_init: Initializing. RAM available for dynamic allocation:e[0m
e[0;32mI (356) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAMe[0m
e[0;32mI (362) heap_init: At 3FFBC608 len 000239F8 (142 KiB): DRAMe[0m
e[0;32mI (368) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAMe[0m
e[0;32mI (374) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAMe[0m
e[0;32mI (381) heap_init: At 4008C8E4 len 0001371C (77 KiB): IRAMe[0m
e[0;32mI (388) spi_flash: detected chip: generice[0m
e[0;32mI (392) spi_flash: flash io: dioe[0m
e[0;33mW (396) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.e[0m
e[0;32mI (410) cpu_start: Starting scheduler on PRO CPU.e[0m
e[0;32mI (0) cpu_start: Starting scheduler on APP CPU.e[0m
Info: lv_init ready (lv_obj.c #231 lv_init())
e[0;32mI (30) lvgl_helpers: Display hor size: 800, ver size: 480e[0m
e[0;32mI (30) lvgl_helpers: Display buffer size: 32000e[0m
e[0;32mI (30) lvgl_helpers: Initializing SPI master for displaye[0m
e[0;32mI (50) lvgl_helpers: Configuring SPI host VSPI_HOST (2)e[0m
e[0;32mI (50) lvgl_helpers: MISO pin: -1, MOSI pin: 13, SCLK pin: 14, IO2/WP pin: -1, IO3/HD pin: -1e[0m
e[0;32mI (60) lvgl_helpers: Max transfer size: 64000 (bytes)e[0m
e[0;32mI (70) lvgl_helpers: Initializing SPI bus...e[0m
e[0;32mI (70) disp_spi: Adding SPI devicee[0m
e[0;32mI (70) disp_spi: Clock speed: 40000000Hz, mode: 0, CS pin: 15e[0m
e[0;32mI (80) RA8875: Initializing RA8875...e[0m
e[0;32mI (290) disp_spi: Changing SPI device clock speed: 1000000e[0m
e[0;32mI (290) gpio: GPIO[15]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0 e[0m
e[0;32mI (290) disp_spi: Adding SPI devicee[0m
e[0;32mI (300) disp_spi: Clock speed: 1000000Hz, mode: 0, CS pin: 15e[0m
e[0;32mI (350) disp_spi: Changing SPI device clock speed: 40000000e[0m
e[0;32mI (350) gpio: GPIO[15]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0 e[0m
e[0;32mI (350) disp_spi: Adding SPI devicee[0m
e[0;32mI (360) disp_spi: Clock speed: 40000000Hz, mode: 0, CS pin: 15e[0m
e[0;31mE (370) spi_master: check_trans_valid(696): SPI half duplex mode does not support using DMA with both MOSI and MISO phases.e[0m
e[0;32mI (380) RA8875: Enabling display.e[0m
e[0;32mI (390) RA8875-Touch: Initializing RA8875 Touch...e[0m
e[0;32mI (390) RA8875-Touch: Enabling touch.e[0m
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: label created (lv_label.c #165 lv_label_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: label created (lv_label.c #165 lv_label_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
Info: Object create ready (lv_obj.c #461 lv_obj_create())
e[0;31mE (480) spi_master: check_trans_valid(696): SPI half duplex mode does not support using DMA with both MOSI and MISO phases.e[0m
I still get a blank screen. I tried both using the RA8875 defaults and using custom pin settings. Kind of weird I can only use either the RA8875 config, XOR custom pins. If I use the latter then I have no choice but to forgo being able to use the touchscreen. But that’s a non-issue at the moment. Just an observation.
Edit: I need to wear my glasses more, because I completely overlooked the pin configuration options for RA8875. Recompiling now and will see what happens.